1. Field of the Invention
The present invention relates to semiconductor packages of CSP (Chip Scale Package) and BGA (Ball Grid Array) structures of a high chip occupying rate and improved in packaging density, and more particularly, to a semiconductor package of a CSP structure and a BGA structure in which reliability as a semiconductor device is prevented from being degraded.
2. Description of the Background Art
A semiconductor package of a CSP structure has been developed as one that can have a high chip occupying rate (more than 90%) and that can have packaging density improved drastically. Such a package is released in, for example, ISSCC (International Solid-State Circuits Conference) 94.
As shown in FIG. 30, a semiconductor package of a CSP structure (referred to as CSP hereinafter) includes a semiconductor chip 1, a connection interconnection 3, a bump electrode 4, and a mold resin 5. Semiconductor chip 1 includes an integrated semiconductor device, and a bonding pad (referred simply as xe2x80x9cpadxe2x80x9d hereinafter) 2 electrically connected to the integrated semiconductor device. Pad 2 is connected to bump electrode 4 via interconnection 3 formed by photolithography. Mold resin 5 covers the entirety thereof except for the head of bump electrode 4. This semiconductor package of a CSP structure is mounted on a predetermined board by fusing bump electrode 4.
Since connection interconnection 3 and bump electrode 4 are formed on semiconductor chip 1 in a CSP, lead pins and wires connecting a lead pin and a pad of a semiconductor chip required in conventional packages do not have to be provided. This eliminates the need of a thick mold that was required to cover the lead pins and wires. Therefore, the thickness of the mold can be reduced significantly. In effect, a CSP allows a package of substantially the same size of a semiconductor chip.
Since interconnection 3 is formed by photolithography, the length and path configuration of connection interconnection 3 can be set arbitrarily. Connection between bump electrode 4 and pad 2 can be implemented easily even when bump electrode 4 and pad 2 are formed at arbitrary positions. Furthermore, wire inductance and input capacitance can be increased to improve electric characteristics by forming interconnecting 3 so that the length between bump electrode 4 and pad 2 is reduced.
FIG. 31 shows a CSP in which connection interconnection 3 is provided with pad 2 arranged at an arbitrary position. As shown in FIG. 31, respective pads 2 are formed at arbitrary positions connected to corresponding bump electrodes 4 by connection interconnection 3 formed vertically and horizontally by photolithography.
As shown in FIG. 31, a CSP can have pad 2, connection interconnection 3 and bump electrode 4 formed on arbitrary positions on a semiconductor chip 1. In forming bump electrode 4 and in mounting the CSP on a board, stress is exerted onto the semiconductor element provided under bump electrode 4. It was therefore necessary to take care that the stress generated in forming bump electrode 4 and in mounting CSP on a board is as low as possible.
The advantage of forming pad 2 or the like at an arbitrary position on semiconductor chip 1 in the CSP was used just for connecting pad 2 with bump electrode 4 by connection interconnection 3 as shown in FIGS. 30 and 31.
In a semiconductor memory such as a DRAM (Dynamic Random Access Memory), the chip area is increased as the capacity thereof becomes greater. However, the demand for increase in speed and reduction in consumption power is insatiable. Increase in the length of the wiring path on a chip due to a larger chip area results in a greater delay in signal transmission to prevent high speed operation.
Furthermore, there is a greater demand for a x16/x32/x64 configuration than a x1/x4/x8 configuration as to the number of data input/output pins corresponding to a multi-bit structure requirement. Increase in the number of bits will require a greater number of output buffers and bonding pads, which in turn will result in a larger chip area. Also, the problem of a power supply noise becomes noticeable.
Furthermore, there is a trend towards a system chip incorporating both memory and logic. Corresponding packaging technology is therefore required.
An object of the present invention is to provide a semiconductor package having a bump electrode arranged taking into consideration stress exerted on an underlying semiconductor element so as to prevent reduction in reliability as a semiconductor device.
Another object of the present invention is to provide a semiconductor package effectively taking advantage of the feature of a CSP.
A further object of the present invention is to provide a semiconductor package that can maintain high speed operation even in a semiconductor memory of a great capacity.
Still another object of the present invention is to provide a semiconductor package that can have increase in chip area and power supply noise suppressed even when the number of bits is increased.
A semiconductor package of the present invention includes features set forth in the following on the postulation that it is a semiconductor package including a plurality of external interconnection units formed of a bump electrode for connection with the outside world, on a main surface of a semiconductor chip having an integrated semiconductor device, a pad formed at the semiconductor chip for connection with the integrated semiconductor device, and a connection interconnection formed on the main surface of the semiconductor chip by photolithography for electrically connecting a pad and a bump electrode.
When an integrated semiconductor device includes a fragile circuit that is easily altered in circuit characteristics by an external factor such as mechanical stress, a semiconductor package according to an aspect of the present invention has a bump electrode formed at a region other than the upper portion of the region where the fragile circuit is provided.
Due to this arrangement, mechanical stress is prevented from being exerted on the fragile circuit via the bump electrode in the semiconductor package of the present aspect.
Preferably, the fragile circuit is a sense amplifier circuit formed of a pair of transistors for sensing and amplifying a small potential difference between a pair of bit lines.
By a virtue of the fragile circuit being a transistor circuit, imbalance in the operation characteristics of the transistor pair due to mechanical stress being exerted via the bump electrode is prevented. Therefore, reduction in the sense operation of the sense amplifier circuit can be prevented.
Preferably, the fragile circuit is an analog circuit operating at a small current.
By virtue of the fragile circuit being an analog circuit, deterioration of the operation of the analog circuit due to mechanical stress being exerted via the bump electrode is prevented.
A semiconductor package according to another aspect of the present invention includes at least one power supply pad, and a power supply interconnection. The power supply pad is provided on a main surface of the semiconductor chip to supply power to an integrated semiconductor device. The power supply interconnection is connected to the power supply pad and is provided so as to surround at least a portion of each of the plurality of external interconnection units.
By virtue of the above-described arrangement, an external interconnection unit surrounded by a power supply interconnection is electrically shielded to be immune from another external internal connection unit and to prevent electrical influence to another external interconnection unit.
Preferably, the power supply interconnection surrounding at least a portion of each of the plurality of external interconnection units is formed in a mesh-like manner connected to each other. A plurality of power supply pads are provided with respect to the mesh-like power supply interconnection so as to reduce the power supply impedance.
By virtue of this arrangement, load of the power supply can be reduced.
Preferably, a stress relaxing material is provided right beneath the bump electrode and between the connection interconnection and the main surface of the semiconductor chip for relaxing mechanical stress exerted on the semiconductor chip via the bump electrode. By virtue of this arrangement, mechanical stress is prevented from being exerted on the integrated semiconductor device.
A semiconductor package according to a further aspect of the present invention has an integrated semiconductor device including an input/output buffer circuit directly connected to a pad. The bump electrode electrically connected to the input/output buffer circuit via the pad is provided above the proximity of the input/output buffer circuit.
By virtue of this arrangement, the interconnection path from the bump electrode and the input/output buffer circuit can be shortened to prevent delay in signal transmission therebetween. Therefore, high speed operation can be maintained even when the capacity of a semiconductor memory or the like is increased. Furthermore, xe2x80x9caddress set upxe2x80x9d and xe2x80x9chold marginxe2x80x9d can be improved due to the reduction of the interconnection path length.
Preferably, the integrated semiconductor device includes a plurality of memory mats, and a master peripheral circuit that divides the plurality of memory mats and controls a memory mat independently. The memory mat includes a plurality of memory regions having a memory element, and a local peripheral circuit dividing the plurality of memory regions and controlling the memory element in each memory region independently.
The integrated semiconductor device has the so-called hierarchical memory structure. Thus, a semiconductor memory of a hierarchical memory structure that can maintain high speed operation even when the capacity is increased can be obtained.
Preferably, a second connection interconnection formed on the main surface of the semiconductor chip is further provided. The master peripheral circuit and the local peripheral circuit are electrically connected by this second connection interconnection.
The second connection interconnection is formed on the main surface of the semiconductor chip. Since elements and circuits are not formed on the main surface of the semiconductor chip, a large line width of the second connection interconnection can be ensured. A material suitable for interconnection can be selected since restriction with respect to the material of the second interconnection is not severe. Therefore, the impedance of the second connection interconnection can be reduced, which in turn allows reduction of the time constant and prevents delay in signal transmission.
Preferably, a bump electrode through which a signal transmitted to each of the plurality of memory mats is entered by the master peripheral circuit is formed on the region where the master peripheral circuit is provided. Each of the plurality of memory mats is arranged so as to be symmetrical with respect to the position of the bump electrode. The interconnection from a bump electrode to the plurality of memory mats is arranged so as to be symmetrical with respect to the position of bump electrode.
By virtue of this symmetrical arrangement, each interconnection from a bump electrode to respective memory mats can be arranged so as to be symmetrical with respect to the bump electrode. An input signal is first entered into the master peripheral circuit that controls each memory mat. Therefore, the transmission distance of a signal from a bump electrode to each of the plurality of memory mats is substantially identical. As a result, phase offset of a signal applied to each memory mat, i.e. the skew, can be reduced significantly.
Preferably, the transmission distance of an input signal from a bump electrode to each of the plurality of memory mats is substantially identical.
Due to this arrangement, the skew for each memory mat can be reduced.
Preferably, an output bump electrode for providing an output signal from a memory element to the outside world is electrically connected to an output buffer provided within a region of the local peripheral circuit. This output bump electrode is arranged on a region where the local peripheral circuit is provided.
The output bump electrode can be arranged in the proximity of the output buffer circuit arranged on a local peripheral circuit region. Therefore, delay of an output signal from an output buffer circuit to a bump electrode can be prevented.
Preferably, the connection interconnection includes first and second connection interconnections electrically insulated from each other, and extending at different levels on the main surface of the semiconductor chip.
By virtue of the first and second connection interconnections extending at different levels, the degree of freedom of the arrangement of the connection interconnection can be increased in comparison with the case where the first and second interconnections are formed on the same level. Therefore, various interconnection structures can be accommodated while maintaining electrical insulation of the first and second connection interconnections.
Preferably, the connection interconnection includes first and second connection interconnections extending on the same level on a main surface of the semiconductor chip. At the crossing of the first and second connection interconnections, the electrical insulation state of the first and second connection interconnections is maintained by one of the first and second interconnections being electrically connected to a conductive layer formed in the semiconductor chip.
Since the first and second connection interconnections extending on the same level can have their insulation state maintained by using a conductive layer in a semiconductor chip, it is easy to comply with various interconnection structures.
Preferably, a power supply bump electrode for supplying power supply to the output buffer circuit is arranged on a region where the local peripheral circuit including the output buffer circuit is provided.
By virtue of this arrangement, power can be supplied from the bump electrode to the output buffer circuit through a short interconnection path. Therefore, a low impedance power supply of low noise can be realized.
Preferably, an output bump electrode electrically connected to each of the plurality of memory elements in a memory region and electrically connected to a data bus for data input/output with the plurality of memory elements is arranged on and in the proximity of the memory region.
By virtue of this arrangement, the data bus can be shortened. Therefore, access will not be degraded even when the number of bits is increased.
Preferably, the master peripheral circuit includes a mat select circuit that selects and renders operable one of the plurality of memory mats, and that inhibits supply of power towards a local peripheral circuit within a non-selected memory mat.
A particular mat can be selected to be rendered operable by the mat select circuit. Since power supply towards the local peripheral circuit is inhibited by a mat select circuit for a non-selected mat, consumption power can be reduced in comparison with the case where a predetermined voltage is applied to a non-selected mat to set a standby state thereof.
Preferably, the master peripheral circuit includes a mat select circuit for selecting and rendering operable a predetermined number of memory mats, and inhibiting power supply into the local peripheral circuit of the non-selected memory mat.
Since the number of memory mats to be selected can be varied according to the mat select circuit, the number of bits can be changed according to the selected number of memory mats. Therefore, the memory size can be set as a variable module. Furthermore, consumption power can be reduced since power supply towards a local peripheral circuit in a non-selected memory mat is prevented by the mat select circuit.
Preferably, a power supply conductive layer for supplying a power supply voltage to elements within the integrated semiconductor device is formed within the semiconductor chip. The connection interconnection to which power supply voltage from the bump electrode is provided extends in a direction crossing the direction of extension of the power supply conductive layer, and is electrically connected to the power supply conductive layer.
By electrically connecting the connection interconnection to the power supply conductive layer, the potential of the power supply conductive layer can be enhanced.
Preferably, the element is a sense amplifier circuit formed of a transistor pair for sensing and amplifying a small potential difference between a bit line pair. The connection interconnection and the power supply conductive layer are arranged so as to be mesh-like in plane.
Since the potential of the power supply conductive layer connected to the sense amplifier circuit is enhanced, a stable operation of the sense amplifier circuit can be achieved.
Preferably, the semiconductor chip includes a test pad for testing brought into contact with a probe needle of a prober in a testing mode. The test pad is provided at the main surface of the semiconductor chip, and is formed on a region other than where the integrated semiconductor device is formed.
The semiconductor chip allows wafer testing by a prober since it includes a pad for testing.
Preferably, an oscillator activated by an external test signal, and a control signal generator for generating various control signals by the oscillator are further provided for a test mode operation. The control signal generator is connected to the master peripheral circuit so that a signal provided from the control signal generator is applied to the master peripheral circuit.
Since a control signal such as RAS and CAS of each address signal and test patterns can be generated in the semiconductor chip by an external test signal, the number of pads for testing can be reduced in comparison with the case where these signals are externally applied to the semiconductor chip.
Preferably, a shift register is further provided for sequentially storing the pass/fail state of test data obtained from each of the plurality of memory mats and sequentially providing the stored pass/fail state of test data.
Preferably, a signal indicating the pass/fail state of test data provided from a shift register is output from the test pad provided in the semiconductor chip.
The pass/fail state of a plurality of test data can be sequentially output to one output pad by the shift register. Therefore, the number of pads required for testing in the semiconductor chip can be reduced.
Preferably, a test pad and a pad are electrically connected to the local peripheral circuit by different interconnection paths. The first interconnection between the test pad and the local peripheral circuit can be switched between a connected and non-connected state. Also, the second interconnection between the pad and the local peripheral circuit can be switched between a connected and non-connected state. In a test mode, the first interconnection attains a connected state, and the second interconnection attains a non-connected state. In a normal operation mode, the first interconnection attains a non-connected state, and the second interconnection attains a connected state.
Since the connection/non-connection of the first and second interconnections can be selected, the test pad can be electrically connected to the local peripheral circuit in a testing mode, and the pad can be electrically connected to the local peripheral circuit in a normal operation mode.
Preferably, a circuit for determining and storing a defective address of a memory element from the pass/fail of test data obtained from each memory mat is further provided. A signal of a defective address is sequentially output from this circuit.
Preferably, a signal of a defective address provided from the circuit that determines and stores a defective address is output from the test pad provided in the semiconductor chip.
The defective address can be output as a packet by the circuit that determines and stores the defective address of a memory element.
Preferably, the power supply interconnection is provided on the main surface of the semiconductor chip so as to surround the interconnection to which a predetermined potential is applied. This power supply interconnection is formed so that current is not conducted.
Due to this arrangement, the interconnection is electrically shielded to be electrically immune from another external interconnection unit and to prevent electrical influence on another external interconnection unit.
Preferably, a plurality of bump electrodes are arranged separated from each other and so as to be exposed from the surface of the entire semiconductor package.
Preferably, the plurality of bump electrodes include a bump electrode which is not electrically connected to a pad.
By virtue of a plurality of bump electrodes formed all over the surface of the semiconductor package, heat radiation of the semiconductor package can be improved. Therefore, the heat resistance can be lowered.
Preferably, a plurality of bump electrodes are also arranged on the back side of the semiconductor package, spaced apart from each other.
By forming bump electrodes also on the back surface, heat radiation of the package can further be improved to reduce heat resistance.
Preferably, a comparator that selects a predetermined number of memory elements from a memory mat to determine match/mismatch of logic of the predetermined number of memory elements, and providing the determination result is connected to only one of the plurality of memory mats.
Since the transmission distance of a signal applied to each of the plurality of memory mats from a bump electrode is substantially equal, the access time towards these mats is also substantially identical. By providing a comparator in only one memory mat and measuring the access time of that memory mat, measurement of the access time period for other memory mats can be omitted. In other words, the so-called I/O false degeneration test is allowed.
A semiconductor package according to still another aspect of the present invention includes a semiconductor chip having an integrated semiconductor device. The integrated semiconductor device includes a plurality of memory mats, and a master peripheral circuit that divides the plurality of memory mats and controls a memory mat independently. A memory mat includes a plurality of memory elements. A circuit for determining and storing a defective address of a memory element from the pass/fail state of test data obtained from each of the plurality of memory mats in a test mode is also provided. A signal of a defective address is sequentially output from this circuit.
By virtue of this circuit for determining and storing a defective address of a memory element, a defective address can be output in a packet.
A semiconductor package according to yet a further aspect of the present invention includes a plurality of external interconnection units formed of a bump electrode on a main surface of a semiconductor chip with an integrated semiconductor device for connection with the outside world, a pad formed on the semiconductor chip for connection with the integrated semiconductor device, and a connection interconnection formed on the main surface of the semiconductor chip by photolithography for electrically connecting a pad and a bump electrode. A power supply interconnection is provided on the main surface of the semiconductor chip so as to surround a connection interconnection to which a predetermined potential is applied. This power supply interconnection is provided so that current is not conducted.
By virtue of this arrangement, this connection interconnection is electrically shielded and is electrically immune to another external interconnection unit and prevents electrical influence to another external interconnection unit.
A semiconductor package according to yet a still further aspect of the present invention includes a pad on a main surface of a semiconductor chip with an integrated semiconductor device. The integrated semiconductor device includes a plurality of memory mats, and a master peripheral circuit dividing the plurality of memory mats and controlling a memory mat independently. A memory mat includes a plurality of memory elements. Each of the plurality of memory mats is arranged so that the transmission distance of a signal applied to each of the plurality of memory mats from a pad is substantially equal. A comparator selecting a predetermined number of memory elements from a memory mat for determining match/mismatch of logic of the predetermined number of memory element and providing the determination result is connected to only one of the plurality of memory mats.
Since the transmission distance of the signal applied to each of the plurality of memory mats from a bump electrode is substantially equal in the semiconductor package, the access time towards these mats is also identical. Therefore, by providing a comparator to one memory mat and measuring the access time of that memory mat, measurement of the access time of the other memory mats can be omitted. In other words, the so-called I/O false degeneracy testing is allowed.
In a semiconductor package according to another aspect of the present invention including a plurality of external interconnection units formed of a bump electrode provided on a main surface of a semiconductor chip including an integrated semiconductor device for connection with an external terminal, a pad formed at the semiconductor chip for connection with the integrated semiconductor device, and a connection interconnection for electrically connecting the pad and the bump electrode, the integrated semiconductor device includes a plurality of memory mats, and a master peripheral circuit for dividing the plurality of memory mats and controlling each memory mat independently. This memory mat includes a plurality of memory arrays, and a local peripheral circuit for dividing the plurality of memory arrays and controlling each memory array independently.
In a semiconductor package according to another aspect of the present invention, a bump electrode is provided for connection with an external terminal such as of a CSP structure and a BGA structure. The bump electrode can be arranged all over the surface of the semiconductor chip. This prevents increase of the size of the semiconductor package such as a QFP and prevents generation of a great capacitance between leads even in the case where hierarchical and highly integrated memories are mounted on a semiconductor package.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.